1. Field of the Invention
The present invention relates to a bias circuit as a reference voltage generator for use with a subranging or two step parallel analog to digital (A/D) converter.
2. Description of the Related Art
In the A/D conversion of an image signal, the conversion speed must be extremely high. The high speed A/D converters currently used are parallel A/D converters, subranging A/D converters, and the like.
It is said that for reproduction of a normal image, 6 bits of a resolution of the A/D converter provide a reproduced image of a tolerable quality, and 7 bits of the resolution provide a reproduced image of a satisfactory quality. At present, the 7-bit resolution of the A/D converter is predominantly employed in the broadcasting system, but high resolution A/D converters of 9 to 10 bits have gradually increased their share of the A/D converters now marketed.
To realize a high precision A/D converter having a resolution of 9 to 10 bits, use of a parallel A/D converter is impractical, because the required number of components, such as comparators and resistors, is increased. The subranging A/D converter may be simplified in circuit construction. In this respect, the subranging A/D converter is suitable for realizing the high precision A/D converter.
Such a subranging A/D converter is discussed by Sugiyama et al. (including the inventor of the present invention) in their paper entitled "Two Step Parallel ADC with Peripheral Analog and Digital Circuit", Technical Report of the Electronic Information Communication Society of Japan, Sept. 22, 1987, pp 13 to 17. In the A/D converter, an analog input signal is compared with the potentials between adjacent resistors of the ladder resistors of a first ladder resistor network (these resistors are connected in series and for generating reference voltages), to thereby determine the upper order bits of a digital value. Then, a potential within a fixed range within which the analog input signal exists is transferred to a second ladder resistor network through analog switches, to thereby determine the lower order bits of the digital value. Thus, it may have the ladder resistors of the second ladder resistor network for common use. Accordingly, the circuit construction of the A/D converter may be simplified.
The A/D converter disclosed in the paper, as shown in FIG. 1, is made up of a first ladder resistor network having resistors R.sub.FO to R.sub.FL, a second ladder resistor network having resistors R.sub.RI to R.sub.RN, analog switches SW for transferring potential within the fixed rang from the first ladder resistor network to the second ladder resistor network, transistors Q.sub.3 and Q.sub.4 for transferring the potential transferred through the switches SW to the second ladder resistor network, comparators COM.sub.X for determining the upper order bits of a digital value, and comparators COM.sub.Y for determining the lower order bits.
To arrange an actual subranging A/D converter, a bias circuit must be coupled with the first and second ladder resistor networks. The bias circuit, as shown in FIG. 1, includes a diode D and transistors Q.sub.1 and Q.sub.2, which make up a mirror circuit, resistors R.sub.00 to R.sub.22, an external terminal T.sub.1 of the IC chip, an externally coupled resistor R.sub.EX, and voltage sources V.sub.(++) and V.sub.(+).
In the subranging A/D converter thus arranged, the comparators COM.sub.X and the first ladder resistor network cooperate to coarsely detect a potential of an analog input signal. The voltage across the ladder resistor located between a comparator COM.sub.X producing a first logic level and a comparator COM.sub.X producing a second logic level, is transferred to the second ladder resistor network, by way of paired switches SW and the transistors Q.sub.3 and Q.sub.4. The comparators COM.sub.Y and the second ladder resistor network cooperate to finely detect the transferred potential.
In the circuit arrangement shown in FIG. 1, to exactly transfer the potential across the ladder resistor R.sub.F, that is selected from among the resistors of the first ladder resistor network, to the second ladder resistor network, the following two conditions must be satisfied.
(1) I.sub.3 =I.sub.4 (The base-emitter voltage V.sub.BEQ3 of the transistor Q.sub.3 =base-emitter voltage V.sub.BEQ4 of the transistor Q.sub.4)
where
I.sub.3 : current flowing through the resistors of the second ladder resistor network, and PA1 I.sub.4 : current flowing through a collector-emitter path of the transistor Q.sub.4. PA1 N : number of the second ladder resistors, PA1 R.sub.R : resistance of each second ladder resistor PA1 R.sub.F : resistance of each first ladder resistor.
(2) I.sub.3 .times.N.times.R.sub.R =I.sub.2 .times.R.sub.F
where
Accordingly, the current condition is given by I.sub.3 =I.sub.4 =(R.sub.F /NR.sub.R)I.sub.2.
A potential difference I.sub.2 .times.R.sub.F, that is transferred from the first ladder resistor network to the second ladder resistor network, is determined by the following facts: 1) the reference current Il is determined by the externally connected resistor R.sub.EX, 2) the current I.sub.2 varies with a variation of the power source voltage, and 3) the ladder resistors R.sub.F are not uniform in resistance, and have a temperature dependency. The variation of the potential difference is undesirable, because it leads to a variation in the dynamic range of the A/D converter, i.e., the voltage range within which the A/D conversion of an analog input signal is allowed.